The present invention relates generally to the field of semiconductor manufacturing. More particularly the present invention relates to a gas baffles and processes for delivering gases used in the formation of integrated circuits.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a film, such as a silicon oxide film, on a semiconductor substrate. Silicon oxide is widely used as a dielectric layer in the manufacture of semiconductor devices. As is well known, a silicon oxide film can be deposited by a thermal chemical-vapor deposition (“CVD”) process or by a plasma-enhanced chemical-vapor deposition (“PECVD”) process. In a conventional thermal CVD process, reactive gases are supplied to a surface of the substrate, where heat-induced chemical reactions take place to produce a desired film. In a conventional plasma-deposition process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film.
Semiconductor device geometries have decreased significantly in size since such devices were first introduced several decades ago, and continue to be reduced in size. This continuing reduction in the scale of device geometry has resulted in a dramatic increase in the density of circuit elements and interconnections formed in integrated circuits fabricated on a semiconductor substrate. One persistent challenge faced by semiconductor manufacturers in the design aud fabrication of such densely packed integrated circuits is the desire to prevent spurious interactions between circuit elements, a goal that has required ongoing innovation as geometry scales continue to decrease.
Unwanted interactions are typically prevented by providing spaces between adjacent elements that are filled with a dielectric material to isolate the elements both physically and electrically. Such spaces are sometimes referred to herein as “gaps” or “trenches,” and the processes for filling such spaces are commonly referred to in the art as “gap-fill” processes. The ability of a given process to produce a film that completely fills such gaps is thus often referred to as the “gap-fill ability” of the process, with the film described as a “gap-fill layer” or “gap-fill film.” As circuit densities increase with smaller feature sizes, the widths of these gaps decrease, resulting in an increase in their aspect ratio, which is defined by the ratio of the gap's height to its depth. High-aspect-ratio gaps are difficult to fill completely using conventional CVD techniques, which tend to have relatively poor gap-fill abilities. One family of dielectric films that is commonly used to fill gaps in intermetal dielectric (“IMD”) applications, premetal dielectric (“PMD”) applications, and shallow-trench-isolation (“STI”) applications, among others, is silicon oxide (sometimes also referred to as “silica glass” or “silicate glass”).
Some integrated circuit manufacturers have turned to the use of high-density plasma CVD (“HDP-CVD”) systems in depositing silicon oxide gap-fill layers. Such systems form a plasma that has a density greater than about 1011 ions/cm3, which is about two orders of magnitude greater than the plasma density provided by a standard capacitively coupled plasma CVD system. Inductively coupled plasma (“ICP”) systems are examples of HDP-CVD systems. One factor that allows films deposited by such HDP-CVD techniques to have improved gap-fill characteristics is the occurrence of sputtering simultaneous with deposition of material. Sputtering is a mechanical process by which material is ejected by impact, and is promoted by the high ionic density of the plasma in HDP-CVD processes. The sputtering component of HDP deposition thus slows deposition on certain features, such as the corners of raised surfaces, thereby contributing to the increased gap-fill ability.
Even with the use of HDP and ICP processes, there remain a number of persistent challenges in achieving desired deposition properties. These include the need to manage thermal characteristics of the plasma within a processing chamber, particularly with high-energy processes that may result in temperatures that damage structures in the chamber and cause contamination. For example, high temperatures have been associated with the formation and sublimation of AlF3, resulting in erosion system components exposed to such high tempratures and deposition of the aluminum impurities on substrates. Fluorine is highly corrosive and often present in chambers a clean gas to corrosively remove material from the chamber wall and also as an etch gas. For example, dissociated NF3 can be introduced into the chamber from a back-side of the baffle to clean the chamber or as an etch component of deposition-etch-deposition recipes which use NF3 plasma within the chamber.
In addition, there is a general desire to provide deposition processes that are uniform across a wafer. Non-uniformities lend to inconsistencies in device performance and may result from a number of different factors. The deposition characteristics at different points over a wafer result from a complex interplay of a number of different effects. For example, the way in which gas is introduced into the chamber, the level of power used to ionize precursor species, the use of electrical fields to direct ions, and the like, may ultimately affect the uniformity of deposition characteristics across a wafer. In addition, the way in which these effects are manifested may depend on the physical shape and size of the chamber, such as by providing different diffusive effects that affect the distribution of ions in the chamber.
Work in relation with embodiments of the present invention suggests the current systems and methods may be less than ideal. For example, as semiconductor circuits and the associated gaps between circuit elements shrink, contamination by small particles can become problematic, especially where the particle size approximates the size of a gap. Also, contamination with metal in the gap fill layer, for example Al, can decrease the desired electrically insulative properties of the dielectric gap-fill layer. This contamination can result in decreased yields, wasted material and in some instances faulty circuits. As a result, one specification of HDP-CVD process films for shallow trench isolation is Al content of the film.
One approach to prevent wafer contamination has been to season the chamber with a protective coating prior to placing a wafer in the chamber. For example, process chambers are often seasoned with a deposition gas, for example SiH4, that deposits a protective coating inside the chamber, for example on the chamber walls, to prevent contamination and protect the chamber from erosion by the clean gas. However, seasoning the chamber with a protective coating takes time, and a typical season time can be on the order of 120 seconds. As a result, the throughput, the number of wafers processed over a given period of time, is decreased, and the throughput of current semiconductor process systems may be less than ideal. Work in relation with the present invention suggests that wafer production throughput can be increased by decreasing the amount of time required to process a wafer, for example by decreasing the season time. Shown in FIG. 1 is an embodiment of a prior art gas baffle that has been used in semiconductor process chambers and shown to present at least some of the shortcomings described above.
There is accordingly a general need in the art for improved systems and methods providing deposition uniformity with decreased contamination from metal atoms, for example aluminum atoms, and increased throughput in HDP and ICP processes.